1. Field of the Invention
The present invention relates generally to a process for manufacturing the dual damascene of semiconductor devices, and more particularly to remove the photoresist layers of the dual damascene.
2. Description of the Prior Art
When semiconductor devices of integrated circuits (IC) become highly integrated, the surface of the chips can not be supplied with enough area to make the interconnects. For matching the requirement of interconnects increases with Complementary Metal-Oxide-Semiconductor (CMOS) devices shrinks, many designs of the integrated circuit have to use dual damascene method. Moreover, it is using the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which is used to separate from each of the interconnects. A conducting wire which connects between the upper and the lower metal layers is called the via plug in semiconductor industry. In general, if an opening, which forms in the dielectric layer exposure to devices of the substrate in, interconnects, it is called the contact hole.
It has two methods for conventional via and interconnect processes, one method is the via and interconnect finish by oneself, wherein the method is that the dielectric is first formed on the metal layer, and then the photoresist layer (PR) is defined on the dielectric, and use the etching process to make the via, and deposit conduction material in the via by means of deposition to finish the via process, then deposit and define metal layer, final, deposit the dielectric layer whereon. Conventional forming metal interconnect process is that make the via and the interconnect by means of two lithography process. Thus, it needs cumbrous steps of deposit and pattern. And yet, it will result in difficult patterned interconnects due to the multi layer connect layout is more daedal in the sub-quarter micron.
Therefore, damascene interconnect structure is developed at present. According to particulars of the process, it will compartmentalize three types, such as the single type, the dual type and the self-aligned type. The damascene is that etch the trench of interconnects in the dielectric, and then fill the metal as interconnect. This method can introduce metal that is difficult etched into the semiconductor without etching in the interconnect process. Therefore, this invention is the best method of the interconnect process in the sub-quarter micron.
The skill of the damascene is a method for forming via and interconnects. In the conventional damascene skill, the remainder of the organic polymer is formed on the photoresist layers after the etching process for forming the trenches. Conventional method for stripping the photoresist layers with the remainder of the organic polymer is plasma treatment with oxygen gas that can effectively strip the photoresist layer without remaining the polymer residues. However, it would induce the trench profile deformation, so that the trench 110 has a bowing profile 120, as shown in FIG. 1. The trench with the bowing profile 120 further leads to the poor deposition of the followed barrier metal and the physical vapor deposition (PVD) process with metal. Especially, in the Copper/chemical vapor deposition inorganic low-K damascene structure, the issues as above are more serious.
In accordance with the above description, a new and improved method for stripping the photoresist layer of the damascene process is therefore necessary, so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a new method for forming the damascene structure is provided that substantially overcomes drawbacks of above mentioned problems raised from the conventional methods.
Accordingly, it is an object of the present invention to provide a new method for stripping the photoresist layer of the damascene process, the present invention can remove the photoresist layer and the polymer residues thereof by a removing process with two steps, so as to avoid the remaining polymer residues and prevent the trench profile from deformation. Furthermore, the removing process with two steps of the present invention utilizes a mixing gas with CF4 to perform an ash process, so as to pre-remove the organic polymer from the surface of the photoresist layer. Then another ash process is performed by way of using another mixing gas with hydrogen to fully remove the photoresist layer. Hence, this invention can effectively raise the quality and the yield of the process, and it also can raise the capability for depositing the followed barrier metal and physical vapor deposition (PVD) process with metal to increase the performance of the device. Therefore, this invention corresponds to economic effect and utilization in industry, and it is appropriate for deep sub-micron technology.
In accordance with the present invention, a new method for removing the photoresist layer of the damascene process is disclosed. First of all, a semiconductor substrate having a dielectric layer thereon is provided. Then a photoresist layer is formed and defined on the dielectric layer. Afterward, an etching process is performed by way of using the photoresist layer as an etching mask to etch through the dielectric layer, so as to form a trench and a polymer layer on the photoresist layer. Subsequently, performing a removing process with two steps strips the photoresist layer and the polymer layer thereof, whereby this removing process with two steps can keep the trench profile and avoid the residues of the polymer layer.